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CD54HC4015 - Dual 4-Stage Static Shift Register

General Description

Maximum Frequency, Typically 60MHz CL = 15pF, VCC = 5V, TA = 25oC Positive-Edge Clocking Overriding Reset Buffered Inputs and Outputs Fanout (Over Temperature Range) - Standard Outputs 10 LSTTL Loads - Bus Driver Outputs

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CD54HC4015, CD74HC4015 Data sheet acquired from Harris Semiconductor SCHS198C November 1997 - Revised May 2003 High Speed CMOS Logic Dual 4-Stage Static Shift Register [ /Title (CD74 HC401 5) /Subject (High Speed CMOS Logic Dual 4- Features Description • Maximum Frequency, Typically 60MHz CL = 15pF, VCC = 5V, TA = 25oC • Positive-Edge Clocking • Overriding Reset • Buffered Inputs and Outputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . .